Moving Past Moore's Law: In-Memory Compute Architecture and Modular Chiplets for Edge Robotics

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For more than half a century, computing progress obeyed Moore's Law: cramming twice as many transistors onto silicon every eighteen to twenty-four months. But in the emerging domain of physical AI and autonomous robotics, Moore's Law has collided with the laws of thermodynamics. Autonomous drones, robotic quadrupeds, surgical manipulators, and self-driving vehicles cannot haul 700-watt server-class GPUs or cooling towers. At the Economist Enterprise Physical AI and Robotics Summit in London on 13 October 2026, Taner Ozcelik, Chairman and Chief Executive of Mythic AI, joined Kenneth Cukier for a fireside chat examining the architectural revolution required to break this deadlock: moving past Moore's Law through analog compute-in-memory (CIM) and modular chiplets.

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The Thermodynamic Wall: Why Physical AI Cannot Live in the Cloud #

During the fireside session titled Moving past Moore’s law: the power behind high-performance robotics, Kenneth Cukier framed the core engineering dilemma confronting enterprise autonomy: artificial intelligence models are expanding in parameter size and perceptual capability, but physical machines operate under ruthless SWaP-C constraints (Size, Weight, Power, and Cost).

Today's AI frontier is anchored in hyperscale data centres drawing 150 megawatts or more across vast server clusters. As Ozcelik pointed out, this architecture operates at energy scales that are millions of times removed from biological reference points. The human brain performs real-time continuous sensorimotor coordination, semantic reasoning, and visual-spatial navigation within a metabolic power envelope of approximately 20 watts.

Historically, robotics engineers attempted to bypass on-board compute limits by offloading inference to the cloud. However, in mission-critical industrial, aerospace, and defence environments, cloud-dependent autonomy is an architectural impossibility:

1. Latency variance and jitter: High-speed closed-loop robotic control requires deterministic motor updates at 50Hz to 1,000Hz (sub-20 millisecond round-trips). Cellular and Wi-Fi networks introduce packet jitter, dropped frames, and latency spikes that cause robotic arms to drop workpieces or autonomous vehicles to fail braking thresholds.
2. Bandwidth saturation: Streaming multiple uncompressed 4K video feeds and LiDAR point clouds from dozens of mobile robots across an industrial plant quickly exhausts local RF bandwidth and incurs exorbitant cloud egress fees.
3. Operational sovereignty and contested connectivity: In underground mining, GPS-denied tunnels, remote construction sites, or tactical military environments, external network links are either non-existent or actively jammed. Autonomous systems must carry complete operational intelligence directly on the edge chassis.

Equipping robots with standard high-performance GPUs brings its own physical penalties: thermal throttling, massive heat sinks that add parasitic payload mass, and high power drain that drains battery flight times from hours to minutes.

The Architectural Thesis: Compute-In-Memory (CIM) #

To solve the thermodynamic bottleneck, Mythic AI has advanced an architectural philosophy: rather than shuttling data between separate processing units and memory pools, the memory itself must become the computer.

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The Physics of Single-Transistor Matrix Multiplication #

In classical digital computing, calculating a matrix dot product requires fetching thousands of 8-bit or 16-bit weight values from external DRAM over high-capacitance bus lines, loading them into cache registers, performing the multiplication inside digital ALUs, and writing results back to memory. Over 90% of the energy is expended in charging and discharging the copper interconnect lines between chips.

In-memory compute architectures replace this digital data transfer with analog circuit physics:

Weight programming. Neural network weights are programmed directly into non-volatile memory cells (such as modified flash or resistive RAM) as analog conductances ($G$). Once programmed, the weights remain stationary inside the memory array; they are never fetched or transferred during inference.

Input voltage modulation. Input activations (such as visual tokens from cameras) are converted into analog voltage levels ($V$) and driven along the array's word lines.

Ohm's Law multiplication. As the input voltage passes through each memory cell, Ohm's Law ($I = V imes G$) performs instantaneous analog multiplication, generating an electric current proportional to the product of the input and the stored weight.

Kirchhoff's Current Law accumulation. Along the vertical bit lines, currents from thousands of parallel memory cells naturally sum together according to Kirchhoff's Current Law ($\sum I = 0$).

A single flash memory array thus executes an entire matrix-vector multiplication in a single clock cycle, operating at the physics level without a single memory fetch. The accumulated analog current is then converted back into digital values via high-speed analog-to-digital converters (ADCs) at the edge of the array.

The Modular Chiplet Strategy #

While analog compute-in-memory solves the energy and latency equations, scaling silicon across diverse commercial domains requires packaging flexibility. Rather than manufacturing large, monolithic system-on-chips (SoCs) - which suffer from exponential defect rates, poor wafer yields, and inflexible product configurations - Ozcelik outlined a modular chiplet strategy.

Under this paradigm, small, standardized in-memory compute tiles are fabricated independently and bonded onto interposers using advanced packaging:

1. Standardized High-Speed Die-to-Die Interconnects: Leveraging emerging standards such as Universal Chiplet Interconnect Express (UCIe), chiplets communicate across micro-bumps with high bandwidth density and picosecond-level latencies.
2. Heterogeneous Composition: A system designer can pair two in-memory chiplets with a low-cost ARM control processor for a lightweight drone payload, or assemble sixteen chiplets alongside high-speed PCIe interfaces to create a server accelerator card for edge data centres.
3. Universal Compilation and Workload Mapping: A unified compiler layer ingests standard deep learning graphs (ONNX, PyTorch) and automatically partitions model layers across the available chiplet topology, optimizing data routing to minimize inter-chiplet communication.

Architectural Comparison: Compute Paradigms for Edge Robotics #

Source: Synthesis of fireside discussion data and semiconductor architecture specifications presented at the Economist Enterprise Physical AI and Robotics Summit (Convene 200 Aldersgate, London, 13 October 2026).

What This Means by Sector #

The commercial validation of in-memory compute depends on penetrating industries where power and cost constraints have historically blocked the deployment of advanced foundation models.

Tactical Defence and Unmanned Systems #

In defence edge applications, energy efficiency translates directly into operational survivability and mission duration. Small unmanned aerial systems (sUAS) and tactical ground rovers are severely constrained by battery weight. Equipping a reconnaissance drone with a conventional GPU cuts its airborne endurance by 30% to 50% simply to power the AI perception stack.

Mythic AI's strategic engagement with Lockheed Martin is focused on embedding in-memory compute into tactical edge systems, autonomous drone swarms, and remote surveillance posts. By reducing compute draw from 50W to under 10W, tactical drones achieve extended flight times while running multi-modal object classification, electronic warfare signal processing, and visual-inertial odometry locally in contested, GPS-denied operational theatres.

Automotive Situational Awareness and In-Cabin AI #

In the automotive sector, tier-one manufacturers face an intense margin squeeze. While flagship electric vehicles can absorb the cost of £2,000 liquid-cooled autonomous driving computers, mass-market vehicles cannot.

Honda Motor's partnership with Mythic AI addresses this commercial friction. Automakers require high-volume, automotive-qualified AI chips costing tens of dollars rather than hundreds, capable of running driver-monitoring systems, blind-spot object segmentation, and 360-degree surround perception without requiring complex liquid cooling loops that add manufacturing cost and assembly complexity.

Industrial Edge Data Centres and Mobile Fulfillment #

While in-memory compute is architecturally optimized for the edge, Mythic is executing a deliberate bridge strategy by offering PCIe accelerator cards for edge data centres and warehouse fulfillment hubs. In facilities hosting hundreds of autonomous mobile robots (AMRs), edge server racks running fleet coordination models are constrained by facility electrical drops and cooling limits. In-memory accelerator cards enable facilities to multiply local inference throughput without upgrading utility power infrastructure.

Supply Chain Resilience and Manufacturing Geography #

A crucial aspect of Ozcelik's briefing centred on supply chain sovereignty. Hardware innovation is meaningless if silicon cannot be reliably fabricated, packaged, and shipped at scale.

Mythic AI has established a distributed international manufacturing footprint:

• Silicon Fabrication: Core in-memory wafer production is anchored in Tokyo, Japan, taking advantage of Japan's established leadership in precision semiconductor fabrication and mature analog/flash process nodes.
• Advanced Packaging and Assembly: Wafers are routed to Europe (specifically Germany) for advanced chiplet dicing, multi-die substrate bonding, and automated optical inspection.
• Revision Validation: The company is currently completing validation of its latest silicon revision, focusing on translating laboratory yield metrics into repeatable, production-grade Statements of Work (SOWs) for automotive and defence volume production.

This multi-region approach avoids single-point geopolitical vulnerabilities while providing European and Asian corporate partners with geographically diversified supply chains.

Conclusion #

The fireside dialogue between Taner Ozcelik and Kenneth Cukier at the Economist Enterprise Physical AI and Robotics Summit outlined the physical reality that will govern the next decade of autonomous systems. Moore's Law, as a simple metric of transistor scaling, is no longer sufficient to power the physical AI revolution.

As long as computing architectures cling to the Von Neumann separation of logic and memory, robotics will remain constrained by battery mass, heat dissipation, and prohibitive bill-of-materials costs. By shifting from digital data movement to analog in-memory compute arrays and modular chiplet topologies, semiconductor engineering is delivering the step-function efficiency breakthrough that autonomous systems require.

The transition from 700W data-centre clusters to 15W edge silicon represents the true gateway to physical autonomy. In the ultimate analysis, robots that operate in the real world must obey the energy laws of the real world; in-memory compute is the architecture that bridges the gap between silicon and biology.

Frequently Asked Questions #

What is the Von Neumann bottleneck in AI hardware? The Von Neumann bottleneck refers to the throughput and energy limitation caused by the physical separation between the central processing unit (ALU) and system memory (DRAM). In artificial intelligence workloads, which involve billions of matrix multiplications, processors spend over 85% of their total energy and substantial clock cycles simply shuttling data back and forth across copper buses, creating severe thermal and latency bottlenecks.

How does analog Compute-In-Memory (CIM) work? Compute-In-Memory performs mathematical operations directly inside memory cells without moving data. Neural network weights are stored as analog conductance states inside non-volatile memory cells. When input voltages are applied across the array, current flows through the cells according to Ohm's Law ($I = V imes G$), and sums along the bit lines according to Kirchhoff's Current Law. This accomplishes complete matrix-vector multiplication in a single physical step.

Why is in-memory compute particularly critical for robotics and drones? Mobile robots and drones operate under strict Size, Weight, Power, and Cost (SWaP-C) limitations. They rely on on-board batteries and cannot support heavy cooling radiators or high-wattage power supplies. In-memory compute provides 10x to 1,000x greater energy efficiency, enabling robots to run complex vision-language-action models locally within a 10W to 20W power envelope while preserving battery endurance.

What is the advantage of a chiplet approach over a monolithic chip? Monolithic chips integrate all functional units on a single, large silicon die. As die size grows, manufacturing defect rates increase exponentially, reducing production yields and raising unit costs. A chiplet architecture breaks the system into smaller, standardized silicon dies that are manufactured independently with high yields and connected via high-speed micro-bumps. This allows modular, flexible configurations tailored to specific industrial power and form-factor requirements.

Who are the primary commercial partners for this technology? Mythic AI's in-memory compute platform is currently anchored by two major corporate partnerships: Lockheed Martin, which is integrating the architecture into tactical defence drones, unmanned robotic platforms, and perimeter security posts to extend battery endurance; and Honda Motor, which is targeting low-cost, automotive-qualified AI chips for vehicle situational awareness and in-cabin sensing.

References #

• Economist Enterprise, (2026). Physical AI & Robotics Summit: Operational advantage through autonomous systems ⧉. Economist Enterprise.
• Ozcelik, T., (2026). Moving past Moore’s law: the power behind high-performance robotics ⧉. Mythic AI.
• Cukier, K., (2026). The Thermodynamic Ceilings on Autonomous Intelligence ⧉. The Economist.
• Marković, D., Mizrahi, A., Querlioz, D., & Grollier, J., (2020). Physics for neuromorphic computing ⧉. Nature Reviews Physics, 2, 499-510.
• Universal Chiplet Interconnect Express, (2025). UCIe Specification 2.0: Die-to-Die Interconnect Standard ⧉. UCIe Consortium.
• IEEE, (2026). International Roadmap for Devices and Systems (IRDS): Beyond CMOS and Compute-in-Memory ⧉. IEEE Standards Association.

கடைசியாக மதிப்பாய்வு செய்யப்பட்டது 2026-10-13.

கடைசியாக மதிப்பாய்வு செய்யப்பட்டது 2026-10-16.

# Moving Past Moore's Law: In-Memory Compute Architecture and Modular Chiplets for Edge Robotics — Sebastien Rousseau

> Originally published at [https://sebastienrousseau.com/ta/2026-10-13-moving-past-moore-law-in-memory/](https://sebastienrousseau.com/ta/2026-10-13-moving-past-moore-law-in-memory/)

At the Economist Enterprise Physical AI and Robotics Summit in London, Mythic AI Chairman and CEO Taner Ozcelik revealed how in-memory compute architecture and modular chiplets are breaking through the Von Neumann memory wall. Learn how transistor-level analog matrix multiplication delivers 10x to 1000x energy efficiency gains for edge robotics, tactical defence, and automotive platforms.

Read the full article on sebastienrousseau.com: https://sebastienrousseau.com/ta/2026-10-13-moving-past-moore-law-in-memory/

Moving Past Moore's Law: In-Memory Compute Architecture and Modular Chiplets for Edge Robotics — Sebastien Rousseau

At the Economist Enterprise Physical AI and Robotics Summit in London, Mythic AI Chairman and CEO Taner Ozcelik revealed how in-memory compute architecture and modular chiplets are breaking through the Von Neumann memory wall. Learn how transistor-level analog matrix multiplication delivers 10x to 1…

https://sebastienrousseau.com/ta/2026-10-13-moving-past-moore-law-in-memory/

Moving Past Moore's Law: In-Memory Compute Architecture and Modular Chiplets for Edge Robotics — Sebastien Rousseau

At the Economist Enterprise Physical AI and Robotics Summit in London, Mythic AI Chairman and CEO Taner Ozcelik revealed how in-memory compute architecture and modular chiplets are breaking through the Von Neumann memory wall.

முக்கிய மூலோபாயக் கருத்துகள் இங்கே:

- The Thermodynamic Wall: Why Physical AI Cannot Live in the Cloud. During the fireside session titled Moving past Moore’s law: the power behind high-performance robotics, Kenneth Cukier framed the core engineering dilemma confronting enterprise autonomy: artificial intelligence…
- The Architectural Thesis: Compute-In-Memory (CIM). To solve the thermodynamic bottleneck, Mythic AI has advanced an architectural philosophy: rather than shuttling data between separate processing units and memory pools, the memory itself must become the computer.
- The Modular Chiplet Strategy. While analog compute-in-memory solves the energy and latency equations, scaling silicon across diverse commercial domains requires packaging flexibility.
- Architectural Comparison: Compute Paradigms for Edge Robotics. Source: Synthesis of fireside discussion data and semiconductor architecture specifications presented at the Economist Enterprise Physical AI and Robotics Summit (Convene 200 Aldersgate, London, 13 October 2026).

இந்தக் கட்டுரையில் விவரிக்கப்பட்ட சவால்களுக்கு உங்கள் நிறுவனத்தின் அணுகுமுறை என்ன?

→ https://sebastienrousseau.com/ta/2026-10-13-moving-past-moore-law-in-memory/

#InMemoryCompute #MythicAi #TanerOzcelik #Moore'sLaw #VonNeumannBottleneck

Sebastien Rousseau | CC-BY-4.0

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Rousseau S. Moving Past Moore's Law: In-Memory Compute Architecture and Modular Chiplets for Edge Robotics — Sebastien Rousseau. sebastienrousseau.com. 2026 Oct 13. Available from: https://sebastienrousseau.com/ta/2026-10-13-moving-past-moore-law-in-memory/

Rousseau, Sebastien. "Moving Past Moore's Law: In-Memory Compute Architecture and Modular Chiplets for Edge Robotics — Sebastien Rousseau." sebastienrousseau.com. October 13, 2026. https://sebastienrousseau.com/ta/2026-10-13-moving-past-moore-law-in-memory/.

Rousseau, S. (2026, October 13). Moving Past Moore's Law: In-Memory Compute Architecture and Modular Chiplets for Edge Robotics — Sebastien Rousseau. sebastienrousseau.com. https://sebastienrousseau.com/ta/2026-10-13-moving-past-moore-law-in-memory/

Moving Past Moore's Law: In-Memory Compute Architecture and Modular Chiplets for Edge Robotics — Sebastien Rousseau

At the Economist Enterprise Physical AI and Robotics Summit in London, Mythic AI Chairman and CEO Taner Ozcelik revealed how in-memory compute architecture and modular chiplets are breaking through the Von Neumann memory wall. Learn how transistor-level analog matrix multiplication delivers 10x to 1000x energy efficiency gains for edge robotics, tactical defence, and automotive platforms.

Originally published at https://sebastienrousseau.com/ta/2026-10-13-moving-past-moore-law-in-memory/ by Sebastien Rousseau.
Licensed under CC-BY-4.0.

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